Phil Bishop, vice president of R&D for high-level synthesis at Cadence, described the efforts at the . Explaining the motivation, he said: “SystemC is often golden at our customers. It’s value proposition is that by keeping things in SystemC you are keeping less code and it's easier to maintain.
High-level synthesis (HLS) promises to deliver complex designs faster and with greater maintainability. Much of the focus has been on using architectural exploration to find ways to create denser logic blocks that meet performance goals. But congestion has emerged as an issue that Cadence Design Systems is addressing with research into its root causes.
As the SoC complexity keeps on increasing and as RTL code size is becoming huge, designing or reusing IPs, verifying them, optimizing them for constraints like area, power, performance while meeting time to market targets is becoming difficult. That leads to serious discussions about moving up one abstraction level above RTL — i.e., to High Level Synthesis (HLS). In this presentation we describe how we used the HLS design flow to design the AXI communication protocol. The AXI model was developed using Synthesizable SystemC Subset, and was synthesized using Cadence Cynthesizer tool to generate the RTL.