The gatelevel netlist from the synthesis tool is taken and imported into place and route tool in Verilog netlist format. All the gates and flip-flops are placed; clock tree synthesis and reset is routed. After this each block is routed. The P&R tool output is a GDS file, used by foundry for fabricating the ASIC. Backend team normally dumps out SPEF (standard parasitic exchange format) /RSPF (reduced parasitic exchange format)/DSPF (detailed parasitic exchange format) from layout tools like ASTRO to the frontend team, who then use the read_parasitic command in tools like Prime Time to write out SDF (standard delay format) for gate level simulation purposes.
Continuous Assignments & Operators
- Detailed discussion of continuous assignments with design examples, followed by an overview of Verilog-2001 operators, also with examples.
Synthesis is the process in which synthesis tools like design compiler or Synplify take RTL in Verilog or VHDL, target technology, and constrains as input and maps the RTL to target technology primitives. Synthesis tool, after mapping the RTL to gates, also do the minimal amount of timing analysis to see if the mapped design is meeting the timing requirements. (Important thing to note is, synthesis tools are not aware of wire delays, they only know of gate delays). After the synthesis there are a couple of things that are normally done before passing the netlist to backend (Place and Route)
Programming Statements & Timescales
- Detailed discussion of blocking and nonblocking assignments, followed by an overview of Verilog-2001 programming statements with examples. This section concludes with a discussion of Verilog timescales and their impact on simulation efficiency.
Save the optimized logic as a structural Verilog file by selectingthe database (".db") file usingthe"menu item. Under the format field, select "VERILOG (v)" for thefile format, and enter the file name "dec2_4_s.v". Then exitdesign_vision using the ""menu command.
Behavioral Commands & Verilog Strengths
- This section details advanced behavioral commands that are sometimes used and abused in models and testbenches. Correct and incorrect usage examples are included.
Duringthe testbench running, the expected output of the circuit is compared withthe results of simulation to verify the circuit design.
File I/O & Testbench Development
- Description of Verilog file I/O commands and usage. Fundamentals of using Verilog file I/O within test environments. Fundamentals of developing self-checking testbenches. Includes a detailed description of stimulus and verification timing.
Simulation is the process of verifying the functional characteristics of models at any level of abstraction. We use simulators to simulate the Hardware models. To test if the RTL code meets the functional requirements of the specification, we must see if all the RTL blocks are functionally correct. To achieve this we need to write a testbench, which generates clk, reset and the required test vectors. A sample testbench for a counter is shown below. Normally we spend 60-70% of time in design verification.
The Synopsys Synthesis Example illustrates that the RTL synthesis is moreefficient than the behavior synthesis, although the simulation of previousone requires a few clock cycles.
Verilog scheduling semantics basically imply a
four-level deep queue for the current simulation time:
1: Active Events (blocking statements)
2: Inactive Events (#0 delays, etc)
3: Non-Blocking Assign Updates (non-blocking statements)
4: Monitor Events ($display, $monitor, etc).
Since the "a = 0" is an active event, it is scheduled into the 1st "queue".
Finally, the display statement is placed into the 4th queue.
A knowledge of digital design engineering. The ability to create files and efficiently use the editors on the operating system used in labs. Without the above skills, students cannot fully benefit from this course. Students will be writing Verilog models for basic and advanced digital circuits such as adders, multiplexers, flip-flops, and shift registers, barrel shifters and a simple DSP processor.
Training is generally conducted at your facilities. For maximum effectiveness, we recommend having one workstation or PC for every two students, with licenses for your preferred Verilog simulator (we often can help provide the simulator and temporary training licenses).
Verilog is such a simple language; you could easily write code which is easy to understand and easy to map to gates. Code which uses if, case statements is simple and cause little headaches with synthesis tools. But if you like fancy coding and like to have some trouble, ok don't be scared, you could use them after you get some experience with Verilog. Its great fun to use high level constructs, saves time.