The results obtained show a significant increase in test application time for low power TPG.
Key words: CUT, LP-TPG, Fault Coverage, Test Cycles, Test Vectors.
 Ajit Pal, Santanu Chattopadhyay, Synthesis and Testing for Low Power, Tutorial T7-A, 2009 22nd International Conference on VLSI Design
 Seongmoon Wang, Srimat T.
Engineering Specialist, Aerospace Corporation: Engineering Specialist, The Aerospace Corporation; works on flexible communications platforms. Founder, fabless semiconductor company developing low-power ASICs for multi-antenna 3G mobile receivers. Research interests: reconfigurable digital signal processing algorithms, low-power VLSI circuits for communications, and system design of wireless data communication systems. BS, EE, Caltech, Ph.D., UCLA.
Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, Humboldt Research Award in 2010, 2010 IEEE Circuits and Systems Society Technical Achievement Award (IEEE Charles Doeser award) , Distinguished Alumnus Award from Indian Institute of Technology (IIT), Kharagpur, Fulbright-Nehru Distinguished Chair, DoD Vannevar Bush Faculty Fellow Faculty Fellow (2014-2019), Semiconductor Research Corporation Aristotle award in 2015, and best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, 2006 IEEE/ACM International Symposium on Low Power Electronics & Design, and 2005 IEEE Circuits and system society Outstanding Young Author Award (Chris Kim), 2006 IEEE Transactions on VLSI Systems best paper award, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design best paper award, 2013 IEEE Transactions on VLSI Best paper award. Dr. Roy was a Purdue University Faculty Scholar (1998-2003). He was a Research Visionary Board Member of Motorola Labs (2002) and held the M. Gandhi Distinguished Visiting faculty at Indian Institute of Technology (Bombay) and Global Foundries visiting Chair at National University of Singapore. He has been in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, and IEEE Transactions on Electron Devices. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000), IEE Proceedings — Computers and Digital Techniques (July 2002), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2011). Dr. Roy is a fellow of IEEE.
This paper explores the energy-delay space of widely referred flip-flops in a 180nm CMOS technology.
Key words: Flip-Flop, Low Power, Pulse triggered, clock gating, SAL technique.
 Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme Yin-TsungHwang; Jin-FaLin; Ming-HwaSheu Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume: 20 , Issue: 2
Rajat Subhra Chakraborty is currently an Associate Professor at CSE Department of IIT Kharagpur. He received his Ph.D. from Case Western Reserve University (U.S.A.) and B.E. from Jadavpur University. He has professional experience of working at National Semiconductor, Bangalore, India and Advanced Micro Devices (AMD), Santa Clara, USA. His research interests include Hardware Security, VLSI Design and Design Automation and Digital Content Protection. He holds 2 Granted U.S. patents, 2 edited volumes, and has co-authored 3 books, 7 book chapters, and over 75 publications in international journals and conferences. His work has received close to 2000 citations till date, and a paper co-authored by him won the Best Paper Award at the IWDW’16 workshop. He has been the Program Chair of SPACE’14, SPACE’15 and AHSA-DSD’17, and regularly features in the program committee of top international conferences. He has received several prestigious international and national awards such as IEI Young Engineers Award (2016), IBM Shared University Research (SUR) Award (2015), Royal Academy of Engineering (U.K.) RECI Fellowship (2014), IBM Faculty Award (2012). Dr. Chakraborty is a Senior Member of IEEE and a Senior Member of ACM.
Professor Abraham’s research interests include VLSI design and test, formal verification, and fault-tolerant computing. He is the principal investigator of several contracts and grants in these areas, and a consultant to industry and government on testing and fault-tolerant computing. He has over 400 publications, and has been included in a list of . He has supervised more than 80 Ph.D. dissertations. He is particularly proud of the accomplishments of his students, many of whom occupy senior positions in academia and industry. He has served as associate editor of several IEEE Transactions, and as chair of the IEEE Computer Society Technical Committee on Fault-Tolerant Computing. He has been elected Fellow of the IEEE as well as Fellow of the ACM, and is the recipient of the 2005 .
Sumeet Kumar Gupta received the B. Tech. degree in Electrical Engineering from the Indian Institute of Technology, Delhi, India in 2006, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from Purdue University, West Lafayette IN in 2008 and 2012, respectively. Dr. Gupta is currently an Assistant Professor of Electrical Engineering at The Pennsylvania State University. Previously, he was a Senior Engineer at Qualcomm Inc. in San Diego CA, where he developed circuit design techniques and benchmarking methodologies of standard cells in deeply scaled technologies. He has also worked as an intern at National Semiconductor, Advanced Micro Devices Inc. and Intel Corporation in 2005, 2007 and 2010, respectively. His research interests include nano-electronics and spintronics, device-circuit-architecture co-design in post-CMOS technologies, low power variation aware VLSI circuit design and nano-scale device-circuit modeling and simulations. He has published over 70 articles in refereed journals and conferences and is a member of IEEE. Dr. Gupta was the recipient of 2016 DARPA Young Faculty Award, an Early Career Professorship by Penn State in 2014, the 6th TSMC Outstanding Student Research Bronze Award in 2012 and Intel Ph.D. Fellowship in 2009. He has also received Magoon Award from the School of Electrical and Computer Engineering, Purdue University, and the Outstanding Teaching Assistant Award from the Teaching Academy and the Office of the Provost, Purdue University, both in 2007. He was awarded a certificate of recognition for outstanding job during the summer internship by Intel Labs and certificates of merit for excellent academic performance at IIT Delhi.
Arijit Raychowdhury is currently an Associate Professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology where he currently holds the ON Semiconductor Junior Research Professorship. He received his Ph.D. degree in Electrical and Computer Engineering from Purdue University. He joined Georgia Tech in January, 2013. His industry experience includes five years as a Staff Scientist in the Circuits Research Lab, Intel Corporation and a year as an Analog Circuit Designer with Texas Instruments Inc. His research interests include digital and mixed-signal circuit design, design of on-chip sensors, memory, and device-circuit interactions. Dr. Raychowdhury holds more than 25 U.S. and international patents and has published over 150 articles in journals and refereed conferences. He is the winner of the NSF CRII Award, 2015; Intel Labs Technical Contribution Award, 2011; Dimitris N. Chorafas Award for outstanding doctoral research, 2007; the Best Thesis Award, College of Engineering, Purdue University, 2007; Best Paper Awards at the International Symposium on Low Power Electronic Design (ISLPED) 2012, 2006; IEEE Nanotechnology Conference, 2003; SRC Technical Excellence Award, 2005; Intel Foundation Fellowship 2006, NASA INAC Fellowship 2004, and the Meissner Fellowship 2002. Dr. Raychowdhury is a Senior Member of the IEEE.
A software package called the TANNER EDA tools utilizing MOSIS 90nm technology is used for the study.
Key words: Flip-flop, low power, pulse-triggered
 Yin-Tsung Hwang, Jin-Fa Lin, and Ming-Hwa Sheu, 2012, "Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme," Proc IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.