It is primarily intended for use in systems where fault is clearing before the first peak of the fault current are required.
Key words: Fault protection, phase-locked loop, power system, fault current limiters,fault current diverters,
This paper presents a comprehensive review of the recently developed phase locked loop and synchronization methods that can be used to discriminate faults from switching transients.
Thispaper presents the design of a wide range voltagecontrolled oscillator, a wide range high speed fullyprogrammable integer N prescaler, a phasefrequency detector (PFD), an accurate chargepump and a loop filter which entails an entire48MHz to 992MHz frequency synthesizer.
Key words: Blind zone, CML Logic, Cycle Slip,Dead zone, Prescalar
 R Jakob Baker, Harry W Li, David E Boyce, "CMOS Circuit Design Layout and Simulation", (Prentice Hall if India, 2003), Ch.
Noise shapingconcentrates the quantization noise produced atthe PFD output into the higher frequencies whereit is removed by the low-pass filter.
Key words: Sigma-Delta modulator; Phase Noise,Phase Locked Loop; Fractional-N FrequencySynthesizer
Design and build a PLL using an active loop filter to meet the folowing specifications: loop crossover frequency:1000 rad/s;phase margin:45°;center frequency:19 kHz;lock range 18 kHz to 20 kHz;steady state error:0;phase detector II
Design and build a circuit to meet the following specifications: loop crossover frequency:1000 rad/s;phase margin:45°;center frequency:19 kHz; lock range 9 kHz to 29 kHz;phase detector II
If you use phase comparator II with just an RC network, be sure to realize that the loop dynamics may be considerably compromised at extremes of lock range.
Specifically, what is the phase detector gain KD, the loop band¬width, the phase margin, the steady state phase error, the lock range, and the ease of acquiring lock (experimentally)?